####################### SELECTING TIMER: ###################### Timer --- Size ----- Conflicts -------------------------- Divisors ------------------------ Features 0 ------- 8-bit ---- millis(), micros(), Arduino Core --- 1,8,64, 256, 1024, external 1 ------- 16-bit --- servo() ---------------------------- 1, 8,64, 256, 1024, external ---- External pin-change capture 2 ------- 8-bit ---- tone() ----------------------------- 1, 8, 32, 64, 128, 256, 1024 TIMER0 ####################### REGISTERS: ###################### TCCR0A - Timer/Counter Control Register A [COM0A1] [COM0A0] [COM0B1] [COM0B0] [] [] [WGM01] [WGM00] RW RW RW RW RW RW TCCR0B - Timer/Counter Control Register B [FOC0A] [FOC0B] [] [] [WGM02] [CS02] [CS01] [CS00] W W RW RW RW RW TCNT0 - Timer/Counter Register (The actual clock value) [TCNT0 7:0] RW OCR1A - Output Compare Register A (The comparison value) The 8-bit comparator continuously compares TCNT0 with the output compare register (OCR0A and OCR0B) [OCR1A 7:0] RW OCR1B - Output Compare Register B (The comparison value) The 8-bit comparator continuously compares TCNT2 with the output compare register (OCR0A and OCR0B) [OCR1B 7:0] RW TIMSK0 - Timer/Coutner2 Interrupt Mask Register [] [] [] [] [] [OCIE0B] [OCIE0A] [TOIE0] RW RW RW TIFR0 - Timer/Counter2 Interrupt Flag Register [] [] [] [] [] [OCF0B] [OCF0A] [TOV0] RW RW RW ####################### BITS: ###################### COM0Ax affects the OC1A pin output COM0Bx affects the OC1B pin output WGM0x affects the Waveform Generation Mode 000 = normal ----------- (TOP=0xFF, OCRx update immediate, TOV Flag set on 0xFF) -- (resets to 0 when it overflows, only TOV2 is triggered) 001 = PWM, phase correct (TOP=0xFF, OCRx update at TOP, TOV Flag set on 0x00) ----- (Timer never resets, oscillates up and down, triggers when it matches OCRx, TOV2 is triggered when it reaches 0) 010 = CTC ------------- (TOP=OCRA, OCRx update immediate, TOV Flag set on 0xFF) -- (resets to 0 when it overflows, triggers when it eaches OCRx) 011 = Fast PWM ---------- (TOP=0xFF, OCRx update 0x00, TOV Flag set on 0xFF) ------- (resets to 0 when it reaches OCRx and triggers) 101 = PWM, phase correct (TOP=OCRA, OCRx update at TOP, TOV Flag set on 0x00) 111 = Fast PWM ---------- (TOP=OCRA, OCRx update 0x00, TOV Flag set on TOP) 100, 110 = Reserved CS0x - Clock Prescaler (Can be changed anytime) 000 = no clock (timer stopped) 001 and up: = /1, /8, /64, /256, /1024, External clock source - Falling Edge, External clock source - Rising Edge 16mHz: 16MHz 2MHz 250kHz 62.5kHz 15,625Hz 62.5ns 500ns 4us 16us 64us Time to ovf: 62.5kHz 7812.5Hz 976.5625Hz 244.140625Hz 61.03515625Hz 16us 128us 1024us 4096us 16384us Phase Correct:31.25kHz 3906.25Hz 488.28125Hz 122.0703125Hz 30.51757813Hz 32us 256us 2048us 9092us 32768us FOC0x - Force a compare match! only active when WGM specifies non-PWM mode OCIE0x - The compare interrupt enable (set when compare is matched) TOIE0 - The overflow interrupt enable OCF0x - The compare interrupt flag TOV0 - The overflow interrupt flag ####################### FUNCTIONS: ###################### ISR(TIMER0_COMPA_vect) { } ISR(TIMER0_COMPB_vect) { } ISR(TIMER0_OVF_vect){ } TIMER1 ####################### GOTCHA: ###################### High bytes of 16-bit registers cannot be read directly. They must be read with entire register. ####################### REGISTERS: ###################### TCCR1A - Timer/Counter Control Register A [COM1A1] [COM1A0] [COM1B1] [COM1B0] [] [] [WGM11] [WGM10] RW RW RW RW RW RW TCCR1B - Timer/Counter Control Register B [ICNC1] [ICES1] [] [WGM13] [WGM12] [CS12] [CS11] [CS10] W W RW RW RW RW RW TCCR1C - Timer/Counter Control Register C [FOC1A] [FOC1B] [] [] [] [] [] [] RW RW TCNT1H - Timer/Counter Register (The actual clock value) [TCNT1 15:8] RW TCNT1L - Timer/Counter Register (The actual clock value) [TCNT1 7:0] RW combined: TCNT1 (MC will modify both registers simultaneously if this is used... There is a temporary register to aid!) OCR1AH - Output Compare Register A (The comparison value) The 16-bit comparator continuously compares TCNT1 with the output compare register (OCR1A and OCR1B) [OCR1A 15:8] RW OCR1AL - Output Compare Register A (The comparison value) The 16-bit comparator continuously compares TCNT1 with the output compare register (OCR1A and OCR1B) [OCR1A 7:0] RW combined: OCR1A??? OCR1BH - Output Compare Register B (The comparison value) The 16-bit comparator continuously compares TCNT2 with the output compare register (OCR1A and OCR1B) [OCR1B 15:8] RW OCR1BL - Output Compare Register B (The comparison value) The 16-bit comparator continuously compares TCNT2 with the output compare register (OCR1A and OCR1B) [OCR1B 7:0] RW combined: OCR1B??? ICR1H - Input Capture Register 1 - updates each time event occurs on ICP1 (or on the analog comparator for timer1) [ICR1 15:8] RW ICR1L - [ICR1 7:0] RW TIMSK1 - Timer/Coutner2 Interrupt Mask Register [] [] [ICIE1] [] [] [OCIE1B] [OCIE1A] [TOIE1] RW RW RW RW TIFR1 - Timer/Counter2 Interrupt Flag Register [] [] [ICF1] [] [] [OCF1B] [OCF1A] [TOV1] RW RW RW ASSR - Asynchronous Status Register [] [EXCLK] [AS2] [TCN2UB] [OCR2AUB] [OCR2BUB] [TCR2AUB] [TCR2BUB] RW RW GTCCR - General Timer/Counter Control Register [TSM] [] [] [] [] [] [PSRASY] [PSRSYNC] RW RW RW ####################### BITS: ###################### COM1Ax affects the OC1A pin output COM1Bx affects the OC1B pin output WGM1x affects the Waveform Generation Mode bits - Mode --------------------- TOP ---- 0CR1x update -- TOV1 Flag Set 0000 = normal ------------------- 0xFFFF - Immed. -------- MAX ---- (resets to 0 when it overflows, only TOV2 is triggered) 0001 = PWM, phase correct 8-bit - 0x00FF - TOP ----------- BOTTOM - (Timer never resets, oscillates up and down, triggers when it matches OCRx, TOV2 is triggered when it reaches 0) 0010 = PWM, phase correct 9-bit - 0x01FF - TOP ----------- BOTTOM - (Timer never resets, oscillates up and down, triggers when it matches OCRx, TOV2 is triggered when it reaches 0) 0011 = PWM, phase correct 10-bit 0x03FF - TOP ----------- BOTTOM - (Timer never resets, oscillates up and down, triggers when it matches OCRx, TOV2 is triggered when it reaches 0) 0100 = CTC --------------------- OCR1A -- TOP ----------- MAX ---- (resets to 0 when it overflows, triggers when it eaches OCRx) 0101 = Fast PWM, 8-bit ---------- 0x00FF - BOTTOM -------- TOP ---- (resets to 0 when it reaches OCRx and triggers) 0110 = Fast PWM, 9-bit ---------- 0x01FF - BOTTOM -------- TOP ---- (resets to 0 when it reaches OCRx and triggers) 0111 = Fast PWM, 10-bit --------- 0x03FF - BOTTOM -------- TOP ---- (resets to 0 when it reaches OCRx and triggers) 1000 = PWM, phase & freq correct ICR1 --- BOTTOM -------- BOTTOM - 1001 = PWM, phase & freq correct OCR1A -- BOTTOM -------- BOTTOM - 1010 = PWM, phase correct ------- ICR1 --- TOP ----------- BOTTOM - 1011 = PWM, phase correct ------- OCR1A -- TOP ----------- BOTTOM - 1100 = CTC --------------------- ICR1 --- Immed. -------- MAX ---- (resets to 0 when it overflows, triggers when it eaches OCRx) 1110 = reserved 1110 = Fast PWM ----------------- ICR1 --- BOTTOM -------- TOP ---- 1111 = Fast PWM ----------------- OCR1A -- BOTTOM -------- TOP ---- ICNC1 - Input Capture Noise Canceller If set to 1, input from input capture pin (ICP1) is filtered - four successive equal samples required to change output ICES1 - Input Capture Edge Select If set to 1, rising edge on ICP1 triggers event. If set to 0, falling edge on ICP1 triggers event. CS1x - Clock Prescaler (Can be changed anytime) 000 = no clock (timer stopped) 001 and up: /1 --------- /8 ------- /64 ------- /256 -------- /1024 ------- External clock source - Falling Edge ---- External clock source - Rising Edge 16mHz: ------- 16MHz ---- 2MHz ----- 250kHz ---- 62.5kHz ----- 15,625Hz -------------- 62.5ns --- 500ns ---- 4us ------- 16us -------- 64us Time to ovf: - ~244.1Hz - ~30.5Hz -- ~3.81Hz --- ~0.954Hz ---- ~0.238Hz --------------- 4,096us -- 32,768us - 262,144us - 1,048,576us - 4,194,304us Phase Correct: ~122Hz -- ~15.3Hz -- ~1.91Hz --- ~0.477Hz ---- ~0.119Hz --------------- 8,092us -- 65,536us - 524,288us - 2,097,152us - 8,388,608us FOC1x - Force a compare match! only active when WGM specifies non-PWM mode ICIE1 - When this bit is written to one, the Timer/Counter1input capture interrupt is enabled. The corresponding interrupt vector is executed when the ICF1 flag, located in TIFR1, is set. OCIE1x - The compare interrupt enable (set when compare is matched) TOIE1 - The overflow interrupt enable ICF1 - The input capture interrupt flag OCF1x - The compare interrupt flag TOV1 - The overflow interrupt flag ####################### FUNCTIONS: ###################### ISR(TIMER1_COMPA_vect) { } ISR(TIMER1_COMPB_vect) { } ISR(TIMER1_OVF_vect){ } TIMER2 ####################### REGISTERS: ###################### TCCR2A - Timer/Counter Control Register A [COM2A1] [COM2A0] [COM2B1] [COM2B0] [] [] [WGM21] [WGM20] RW RW RW RW RW RW TCCR2B - Timer/Counter Control Register B [FOC2A] [FOC2B] [] [] [WGM22] [CS22] [CS21] [CS20] W W RW* RW* RW RW *Typo in Datasheet https://forum.arduino.cc/index.php?topic=150642.0 TCNT2 - Timer/Counter Register (The actual clock value) [TCNT2 7:0] RW OCR2A - Output Compare Register A (The comparison value) The 8-bit comparator continuously compares TCNT2 with the output compare register (OCR2A and OCR2B) (pp 118) [OCR2A 7:0] RW OCR2B - Output Compare Register B (The comparison value) The 8-bit comparator continuously compares TCNT2 with the output compare register (OCR2A and OCR2B) (pp 118) [OCR2B 7:0] RW TIMSK2 - Timer/Coutner2 Interrupt Mask Register [] [] [] [] [] [OCIE2B] [OCIE2A] [TOIE2] RW RW RW TIFR2 - Timer/Counter2 Interrupt Flag Register [] [] [] [] [] [OCF2B] [OCF2A] [TOV2] RW RW RW ASSR - Asynchronous Status Register [] [EXCLK] [AS2] [TCN2UB] [OCR2AUB] [OCR2BUB] [TCR2AUB] [TCR2BUB] RW RW GTCCR - General Timer/Counter Control Register [TSM] [] [] [] [] [] [PSRASY] [PSRSYNC] RW RW RW ####################### BITS: ###################### COM2Ax affects the OC2A pin output COM2Bx affects the OC2B pin output WGM2x affects the Waveform Generation Mode 000 = normal ----------- (TOP=0xFF, OCRx update immediate, TOV Flag set on 0xFF) -- (resets to 0 when it overflows, only TOV2 is triggered) 001 = PWM, phase correct (TOP=0xFF, OCRx update at TOP, TOV Flag set on 0x00) ----- (Timer never resets, oscillates up and down, triggers when it matches OCRx, TOV2 is triggered when it reaches 0) 010 = CTC ------------- (TOP=OCRA, OCRx update immediate, TOV Flag set on 0xFF) -- (resets to 0 when it overflows, triggers when it eaches OCRx) 011 = Fast PWM ---------- (TOP=0xFF, OCRx update 0x00, TOV Flag set on 0xFF) ------- (resets to 0 when it reaches OCRx and triggers) 101 = PWM, phase correct (TOP=OCRA, OCRx update at TOP, TOV Flag set on 0x00) 111 = Fast PWM ---------- (TOP=OCRA, OCRx update 0x00, TOV Flag set on TOP) 100, 110 = Reserved FOC2x - Force a compare match! only active when WGM specifies non-PWM mode CS2x - Clock Prescaler (Can be changed anytime) 000 = no clock (timer stopped) 001 and up: = /1, /8, /32, /64, /128, /256, /1024 16mHz: 16MHz 2MHz 500kHz 250kHz 125kHz 62.5kHz 15,625Hz 62.5ns 500ns 2us 4us 8us 16us 64us Time to ovf: 62.5kHz 7812.5Hz 1953.125Hz 976.5625Hz 488.28125Hz 244.140625Hz 61.03515625Hz 16us 128us 512us 1024us 2048us 4096us 16384us Phase Correct:31.25kHz 3906.25Hz 976.5625Hz 488.28125Hz 244.140625Hz 122.0703125Hz 30.51757813Hz 32us 256us 1024us 2048us 4096us 9092us 32768us OCIE2x - The compare interrupt enable (set when compare is matched) TOIE2 - The overflow interrupt enable OCF2x - The compare interrupt flag TOV2 - The overflow interrupt flag ####################### FUNCTIONS: ###################### ISR(TIMER2_COMPA_vect) { } ISR(TIMER2_COMPB_vect) { } ISR(TIMER2_OVF_vect){ } Watchdog Timer ####################### REGISTERS: ###################### WDTCSR - Watchdog Timer Control Register [WDIF] [WDIE] [WDP3] [WDCE] [WDE] [WDP2] [WDP1] [WDP0] All RW WDIF = Watchdog Interrupt Flag, set when Interrupt is called (NOT reset) WDIE = Watchdog Interrupt Enable WDE = Watchdog System Reset Enable WDCE = allow configuration for 4 clock cycles Timeout (ms) - 16 - 32 - 64 - 125 - 250 - 500 - 1000 - 2000 - 4000 - 8000 WDP ---------- 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 Action on Timeout --- WDTON - WDE - WDIE None ---------------- 1 ----- 0 --- 0 Interrupt ----------- 1 ----- 0 --- 1 Reset --------------- 1 ----- 1 --- 0 Interrupt, then reset 1 ----- 1 --- 1 Reset --------------- 0 ----- x --- x NOTE: WDTON is a fuse ####################### CODE: ###################### #include cli(); //Disable all interrupts WDTCSR |= (1<